1. Field of the Invention
The present invention relates generally to translation circuits and, in particular, to circuits suitable for translating Current Mode Logic (CML) level signals to Complementary Metal Oxide Semiconductor (CMOS) level signals.
2. Description of Related Art
In digital systems using logic circuitry from different types of logic families, it is necessary to translate one logic level to another. By way of example, logic levels used in Current Mode Logic (CML) circuits, such as Emitter Coupled Logic (ECL), frequently have to be translated to logic levels used in Complementary Metal Oxide Semiconductor (CMOS) circuits. ECL is typically utilizes when high speed is desired and where relatively high power consumption can be tolerated. CMOS is typically used where speed is not of paramount concern, but low power consumption is needed. ECL is implemented using bipolar transistors and CMOS is implemented using MOS transistors. When it is necessary to provide an interface between the two types of circuit families, it is common to use BiCMOS technology which combines both bipolar and MOS transistors. Note that the term MOS is used herein to include all types of insulated gate field effect transistors including both metal and silicon gate devices.
Referring to the drawings, FIG. 1 is a schematic diagram of a conventional ECL to CMOS converter circuit using BiCMOS technology. The input Vin is produced by ECL circuitry and typically has a small voltage swing of only 0.8 volts. Although ECL is frequently powered from negative supplies, the exemplary circuit of FIG. 1 uses a +5 volt supply. CMOS voltage swings are typically from rail to rail so that there will be a 5 volt swing when a single +5 volt supply is used.
The FIG. 1 circuit includes an ECL buffer circuit which includes differentially-connected NPN transistor 10 and 12 having their emitters connected to a common current source 14A. The ECL input Vin is buffered by a pair of emitter-follower stages including transistor 20 in combination with current source 14B followed by transistor 22 in combination with current source 14C. Thus, the voltage applied to the input of the differential amplifier, the base of transistor 10, will still have a voltage swing of 0.8 volts since the emitter follower stages each have unity voltage gain. The remaining input to the differential amplifier, the base of transistor 12, is connected to a reference voltage Vref. Vref is selected such that the voltage falls at the center of the voltage swing present at the base of transistor 10, that being equal to the center of the swing.
When Vin is at the maximum value, transistor 10 is turned on and transistor 12 is off. Thus, all current provided by source 14A will flow through load resistor 16. The magnitude of current source 14A and resistor 16 (also resistor 18) are selected such that the voltage at the collector of transistor 10 will not drop sufficiently low to permit transistor 10 to go into saturation thereby assuring high speed operation. At no time should the transistor 10 collector voltage (or the transistor 12 collector voltage) be permitted to drop below Vref. Since transistor 12 is off, the collector of the transistor will be almost at voltage V.sub.DD. When Vin is at a minimum value, transistor 10 is turned off so that all current from source 14A will flow through resistor 18. Thus, the differential output of the differential stage, the collectors of transistors 10 and 12, will have a voltage swing that is still fairly small with respect to V.sub.DD and will be roughly 2.0 volts.
The differential outputs of the buffer stage are each connected to respective inputs of a pair of emitter-follower circuits including transistor 24 operating in combination with current source 14D and transistor 26 operating in combination with current source 14E. The follower outputs are connected to the respective gates of P-type MOS transistors 28 and 30. The drain of transistor 28 is connected to the input half of a current mirror circuit, namely, the gate and drain of an N-type transistor 32. The drain of transistor 30 is connected to the drain of transistor 34 which forms the output half of the current mirror circuit.
When the input to the gate of transistor 28 drops and the input to the gate of transistor 30 is raised, transistor 28 is turned on and transistor 30 is turned off. Current flow in transistor 28 causes flow in transistor 34, with this current being mirrored into transistor 34. Since transistor 30 is off, the drain of transistor 34, the output of the circuit, will be pulled down to ground potential. Similarly, if the inputs cause transistor 28 to turn off and transistor 30 to turn on, current through 32 will stop. This lack of current will be reflected in the current mirror so that transistor 34 will turn off. This combination will cause the drain of transistor 30, the circuit output, to approach the supply voltage V.sub.DD. Thus, the output is CMOS compatible.
FIG. 2 is another exemplary ECL to CMOS converter circuit using BiCMOS technology. In this case. the ECL input happens to be a differential input Vin and Vin. The ECL input maximum value will typically be on the order of one diode drop (0.7 volts) below V.sub.DD. An NPN transistor 36, P-type MOS transistor 35 and current source 39 form a biasing circuit 37. The base of transistor 36 is connected to a bias voltage V.sub.B which is typically set to be near the high point of the voltage swing of Vin and Vin. Transistor 35 will thus conduct the current drawn by source 39 and operate to bias the gates of N-type MOS transistors 40A, 40B, 40C and 40D at a fixed voltage notwithstanding changes in the supply voltage V.sub.DD.
Input Vin is connected to bases of bipolar transistors 38A and 38B and complementary input Vin is connected to the bases of transistors 38C and 38D so as to form four emitter follower circuits. The outputs of the emitter followers are connected to the respective sources of transistors 40A, 40B, 40C and 40D. The drain of transistor 40A is connected to the input half of a first current mirror, namely the drain and gate of N-type transistor 42. Similarly, the drain of transistor 40D is connected to the input half of a second current mirror, namely the drain and gate of N-type transistor 42D.
The drain of transistor 40C is connected to the first current mirror output, the drain of N-type transistor 42A. The drain of transistor 40B is connected to the second current mirror output, the drain of N-type transistor 42C. The drain of transistor 42C also functions as the output Vout of the circuit, with the drain of transistor 42B functioning as the inverted output Vout.
When Vin is at a maximum value, the source voltage of transistors 40A and 40B are increased. At the same time Vin will be at a minimum value so that the transistor 40C and 40D source voltages will be at a minimum value. The gate voltages of the four P-type transistors will be held at a constant voltage by biasing circuit 37, midway between the increased source voltage of transistors 40A and 40B and the decreased source voltage of transistors 40C and 40D. Under these conditions, transistors 40A and 40B will be on and transistors 40C and 40D will be off.
Transistor 40A will conduct a current which will be mirrored by transistor 42A into transistor 42B thereby causing transistor 42B to be conductive. At the same time, transistor 40C will be off, so that the drain of transistor 42B, the inverted output Vout, will be pulled down to ground potential (V.sub.SS). Transistor 40D will be off so that the current input to the second mirror will be zero thereby causing mirror output transistor 42C to be off. Since transistor 40B is on, the circuit output Vout will be pulled to a high voltage approaching Vin less the base-emitter voltage V.sub.BE of transistor 38B. When Vin and Vin change state, transistors 40A and 40B will turn off and transistors 40C and 40D will turn on thereby causing the second current mirror to become active so that Vout will be at ground potential and Vout will be pulled up to a high voltage by transistor 40C approaching Vin minus the base-emitter voltage V.sub.BE of transistor 38C.
A principal disadvantage of the FIG. 1 and FIG. 2 prior art translating circuits is the relatively small magnitude of the drive voltage to the P-type transistors. In the FIG. 1 circuit, for example, the source voltage is fixed at V.sub.DD and the gate drive voltages applied to transistors 28 and 30 only change a small amount roughly equal to the difference in voltage between V.sub.DD and Vref. In the FIG. 2 circuit, the gates of the P-type transistors 40A, 40B, 40C and 40D are held constant, with the source drive voltage swing being equal to the relatively small change in input voltage Vin (or Vin).
The relatively small P-type transistor drive voltage of the prior art circuits results in reduced operating speed. This reduction in speed can be offset by increasing the magnitude of current used in the circuits but this results in undesirable increased power consumption. Further, an additional voltage gain stage could be added to increase speed, but this would also increase power consumption and increase circuit complexity.
There is a need for a translator circuit capable of achieving relatively high speed operation without incurring undue power consumption. The present invention provides this advantage along with additional advantages that will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.